The present invention relates to an improved data processor implemented as CPU or microprocessor, for example, and more particularly relates to a data processor adapted for use with an instruction set suitable for downsizing a program.
As semiconductor technologies and architecture of processors have been vigorously researched and developed over the past few years, the performance of programmable data processors of various types, termed xe2x80x9cCPU""sxe2x80x9d, have also been tremendously improved. Depending on their specific applications, CPU""s may be roughly classified into the following two types: general-purpose microprocessors; and built-in microcontrollers for use in numerous kinds of control units and consumer electronics appliances. As for CPU""s of the first type, that is, general-purpose microprocessors, improvement of performance is a top priority. Therefore, for the sake of improving the performance of general-purpose microprocessors, a wide variety of techniques have heretofore been employed. In contrast, with regards to built-in microcontrollers, it is true that improvement of performance is one of most significant objects to be achieved. What is more important is, however, striking an appropriate balance among performance improvement, cost effectiveness and reduction in power consumption. Among other things, the cost effectiveness plays a key role in meeting a high demand in consumer electronics applications.
There are two tips for realizing a CPU at a lower cost: reducing the size of a CPU itself (i.e., reducing the area of a CPU core); and shrinking the size of a program (or the size of a ROM). In recent years, as the performance of a CPU has been improved, the number of functions implementable by a single CPU has increased and the size of an application program has further increased correspondingly. Under the circumstances such as these, the size of a ROM for storing such a large-sized program dominates over the area of a CPU core. Accordingly, the cost effectiveness of a CPU is greatly dependent on how small the size of a program, applicable to the CPU, can be.
The prior art, developed to solve this task, will be described. In accordance with this technique, the architecture of an instruction set for a general-purpose microprocessor is extended to reduce the size of a program.
FIG. 22 illustrates examples of MIPS architecture instruction format for a data processor in the pertinent prior art. specifically, FIG. 22(a) illustrates a MIPS-II/III instruction format used for executing a register-to-register instruction where the length of a basic instruction word (hereinafter, simply referred to as a xe2x80x9cbasic instruction lengthxe2x80x9d) is fixed at 32 bits. In contrast, FIG. 22(b) illustrates MIPS16 instruction formats where the basic instruction length is fixed at 16 bits.
In accordance with the MIPS architecture, 32 registers are provided. Thus, an instruction set in the MIPS-II/III format includes a plurality of register-addressing fields each composed of 5 bits. Also, since three operands are specified according to the MIPS-II/III format, this instruction set includes three register-addressing fields rs, rt and rd. The operation and functions of the instruction are defined using a 6-bit OP field, a 5-bit shamt field and a 6-bit func field. Accordingly, this instruction set has a fixed length of 32 bits in total.
In contrast, two types of instruction formats are definable for a register-to-register instruction included in an instruction set according to the MIPS16 format. In one of the two types of instruction formats, two 3-bit register-addressing fields rx and ry are provided to specify two operands and the operation and function of the instruction are defined using a 5-bit OP field and a 5-bit func field. In he other instruction format, three 3-bit register-addressing fields rx, ry and rz are provided to specify three operands and the operation and function of the instruction are defined using a 5-bit OP field and a 2-bit F field.
In accordance with the MIPS16 format shown in FIG. 22(b), only 3 bits are available for each register-addressing field. Accordingly, not all the 32 registers included in the original MIPS-II/III format, but some of these registers can be accessed.
Any instruction in the MIPS16 instruction format can be replaced with an associated instruction in the MIPS-II/III instruction format. Such replacement of an instruction in the MIPS16 instruction format with a counterpart in the MIPS-II/III instruction format is called an xe2x80x9cextensionxe2x80x9d of an instruction.
FIG. 23 is a block diagram illustrating a main part of a data processor for executing instructions in the MIPS16 and MIPS-II/III formats. Hereinafter, the operation of this data processor will be described.
An instruction fetch section 300 is a block for fetching an instruction. Specifically, the instruction fetch section 300 fetches an instruction set in the MIPS16 instruction format with a fixed length of 16 bits or in the MIPS-II/III instruction format with a fixed length of 32 bits, and then outputs the fetched instruction set to an instruction extender 310. The type of the instruction set, i.e., whether the instruction set is in the MIPS16 or MIPS-II/III instruction format, is always specified by a mode setting signal.
The instruction extender 310 is also controlled by the mode setting signal. If the input instruction set is in the MIPS16 instruction format, then the instruction extender 310 extends the instruction set in the MIPS16 instruction format into that in the MIPS-II/III instruction format. Alternatively, if the input instruction set is in the MIPS-II/III instruction format, then the instruction extender 310 outputs the instruction set as it is without performing the extension. It is controlled by the mode setting signal whether or not the extension should be performed. Accordingly, the instruction extender 310 cannot determine the necessity from the instructions themselves. Since the mode setting signal is a programmable signal, the mode of operations can be switched at a desired time.
An instruction decoder 320 is a block for decoding the instruction in the MIPS-II/III instruction format and thereby producing a control signal. The operation of the data processor is controlled by the control signal produced by the instruction decoder 320.
The data processor having such a configuration can execute both a program described in the MIPS16 instruction format with a basic instruction length of 16 bits and a program described in the MIPS-II/III instruction format with a basic instruction length of 32 bits. Accordingly, if the code size should be prioritized, then programming is preferably carried out using the MIPS16 instruction format with a fixed length of 16 bits. On the other hand, if the performance should be respected first to access as large a number of register files as possible, then programming may be conducted using the MIPS-II/III instruction format. Thus, a program can be developed flexibly with a good balance struck between performance and code size. Nevertheless, it depends sometimes on the specifications of a particular system and sometimes on the size of a program which type of instruction formats should be used. For example, a certain type of format is used only when the size of a program reaches that of a task.
In order for a microprocessor to perform such an application (like signal processing) as requiring a large number of registers, the number of available registers should preferably be increased by adding some registers to preexistent ones such that the application can be performed at an even higher speed. In such a case, an instruction format, allowing the user to specify a larger number of registers than a conventional instruction format, may be produced and used instead of the conventional instruction format. However, the size of a resultant program considerably increases by the use of such an alternate instruction format.
Thus, the prior art may be modified in the following manner. A new instruction format, allowing the user to specify a larger number of registers, may be provided in addition to the conventional instruction format. And the newly provided instruction format and the conventional instruction format may be selectively employed in response to the mode setting signal of the prior art.
Nevertheless, if the mode setting signal of the prior art is used, then the code size still increases disadvantageously. That is to say, a switching instruction should be given to generate the mode setting signal in switching the instruction formats. Accordingly, if a plurality of instructions, described in these formats, are included within a single instruction set, then the switching instructions should also be given numerous number of times, thus adversely increasing the code size.
An object of this invention is providing a data processor allowing for the use of additional registers to execute instructions in several types of instruction formats included within a single instruction set and to switch these formats without the mode setting signal while effectively reducing the code size.
To achieve this object, according to the present invention, a first instruction format, allowing the user to specify a number of registers, and a second instruction format, allowing the user to specify a larger number of registers than that of the registers specified in the first instruction format, are used. The types of instructions, described in these formats, are identifiable by the instructions themselves. Accordingly, an application requiring a large number of registers, like signal processing, can be performed at a higher speed without increasing the code size.
Specifically, a data processor according to the present invention executes an instruction described in a first instruction format and an instruction described in a second instruction format. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than the size of the register-addressing field defined by the first instruction format. The data processor includes: means, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than the number of the registers included in the first register file. If the identifying means has identified the received instruction as being described in the first instruction format, the data processor executes the instruction using data held in the first register file. On the other hand, if the identifying means has identified the received instruction as being described in the second instruction format, the data processor executes the instruction using data held in the second register file.
In one embodiment of, the present invention, the first instruction format defines a number of instruction fields and the second instruction format defines another number of instruction fields. And the identifying means identifies the received instruction as being described in the first or second instruction format by the contents of at least one of the instruction fields of the instruction that is defined by at least one predetermined ordinal number.
In another embodiment of the present invention, the number of the instruction fields defined by the second instruction format is larger than the number of the instruction fields defined by the first instruction format.
In still another embodiment, the predetermined ordinal number of the instruction field used by the identifying means for format identification is first.
In still another embodiment, the second register file includes all of the registers included in the first register file.
In still another embodiment, the data processor further executes an instruction described in a third instruction format. The third instruction format specifies a plurality of operations and defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The register-addressing field defined by the third instruction format is used to specify one of the registers included in the second register file. Responsive to an instruction, the identifying means identifies the received instruction as being described in the third instruction format by the instruction itself.
Another data processor according to the present invention also executes an instruction described in a first instruction format and an instruction described in a second instruction format. The data processor includes: a register file including a predetermined number of registers, an address described in the first instruction format for specifying one of the registers being different from an address described in the second instruction format for specifying the same register; an address converter for receiving the instruction described in the first instruction format and converting an address described in the first instruction format, specified by the instruction to access one of the registers, into an address described in the second instruction format; and means, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself. The output of the address converter is controlled by the output of the identifying means.
According to the present invention, an instruction format is provided for use in defining an arrangement of an instruction to be executed by a data processor. The instruction format is implemented as first and second instruction formats. The first instruction format defines a number of instruction fields and the second instruction format defines another number of instruction fields, the number of the instruction fields defined by the second instruction format being larger than the number of the instruction fields defined by the first instruction format. At least one of the instruction fields that are defined by the first and second instruction formats is used to identify the type of the instruction to be executed as being described in the first or second instruction format. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than the size of the register-addressing field defined by the first instruction format.
In one embodiment of the present invention, the instruction format is implemented as a third instruction format. The third instruction format defines still another number of instruction fields, the number of the instruction fields defined by the third instruction format being larger than the number of the instruction fields defined by the first instruction format. The third instruction format defines a register-addressing field of a size larger than the size of the register-addressing field defined by the first instruction format. At least one of the instruction fields that are defined by the third instruction format is used to identify the type of the instruction to be executed as being described in the third instruction format. And the third instruction format describes a plurality of operations to be executed.
According to the present invention, the instruction itself is input to the identifying means, which identifies the instruction format thereof. In this case, the identifying means identifies the instruction format of the received instruction by the instruction itself, e.g., the contents of the first instruction field of the instruction. Accordingly, unlike the prior art, there is no need to use any special instruction to generate a mode setting signal or the like and the code size does not increase in vain. Accordingly, it is possible to effectively reduce the size of a program while allowing the user to execute a plurality of instructions described in several types of instruction formats included within a single instruction set.
In addition, in executing an instruction described in the first instruction format, a register to be accessed is specified from only a smaller number of registers included in the first register file. On the other hand, in executing an instruction described in the second instruction format, a register to be accessed can be specified from a larger number of registers included in the second register file. In this manner, arithmetic operations using these many registers can be described within a single instruction. Accordingly, the memory does not have to be accessed so frequently and data can be processed faster.
As can be understood, the present invention makes it possible to increase the number of usable registers and the speed of data processing while effectively reducing the size of a program.
Moreover, in accordance with the present invention, a plurality of operations can be specified within a single instruction described in the third instruction format. Accordingly, these operations, defined within a single instruction, can be performed in parallel, thus increasing the speed of data processing even more.
Furthermore, even if a bit assignment on the instruction code used to specify a register in the first instruction format is different from that used to specify the same register in the second instruction format, these bit assignments can be equalized through the address conversion by the address converter. Accordingly, complete compatibility can be maintained between a plurality of instruction formats, i.e., an instruction set described in one of the instruction formats can be executed without rewriting the instruction set into another instruction format.